Checking¶

astli check performs whole-design semantic analysis, checking your SystemVerilog source files with the rigor of a production compiler frontend.

astli check -f src.f                  # Check a design defined by a filelist
astli check +incdir+include rtl/*.sv  # Check files with include search paths
astli check -f src.f --top soc_top    # Hierarchically elaborate and check from a top module
astli check                           # Automatically check the current package and its dependencies

astli check compiles and links the design across all source files, identifying standard IEEE 1800 compliance violations:

• Missing definitions: References to undeclared signals, types, packages, or missing module definitions.
• Port and parameter mismatches: Port connections or parameter overrides that do not exist on the target module, positional argument counts exceeding definitions, or duplicate connections.
• Illegal multiple drivers: SystemVerilog variables concurrently driven by multiple procedural blocks (always_comb, always_ff), continuous assign statements, or module output ports.

A comprehensive list of diagnostics and error codes is available in the Check Diagnostics Reference.

Conservative error reporting ("Only what is certain")¶

A core design principle of astli check is zero false positives. It aims to report only genuine errors that would fail a conforming IEEE 1800 compiler, avoiding speculative warnings when code constructs cannot be fully evaluated.

Where static analysis lacks complete information, astli behaves conservatively:

• Generate constructs without --top: When running without an explicit --top module, astli cannot know which generate branches are active. Instantiations inside generate blocks are therefore checked leniently; missing module definitions within unelaborated generate branches emit warnings rather than fatal errors.
• Hierarchical elaboration with --top: When --top is specified, astli evaluates branch conditions and loop ranges (genvar). Modules in active generate branches are rigorously checked, while inactive branches are pruned.
• Unresolved includes or syntax errors: If an `include file is missing or a file contains syntax errors, astli flags the error but avoids cascading false undeclared-variable errors for downstream code that might have been defined in that missing header.
• Hierarchical scopes: Deeply nested struct fields, dynamic class properties, and hierarchical identifiers (e.g. u_sub.reg_field) are checked at their root symbol without false alarms on unmodeled sub-properties.

Inspecting the hierarchy with astli elab¶

You can visualize the elaborated module hierarchy using astli elab:

astli elab -f src.f --top soc_top

astli elab builds the full instance tree and prints a clean ASCII hierarchy showing:

• Every instantiated module, interface, and block instance path.
• Parameter values that have been overridden from their defaults.
• Active generate blocks, conditionally selected branches, and unrolled loops.
• Flagged instances referencing missing definitions or unresolved parameters.